2024:

1. HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices.. Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu, IEEE Transactions on Computers (TC), 2024.
   
2. Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems. Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu, ACM/IEEE Design Automation Conference (DAC), 2024.
   
3. Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao, ACM/IEEE Design Automation Conference (DAC), 2024.
   
4. GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration. Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu, ACM/IEEE Design Automation Conference (DAC), 2024.
   
5. WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA.. Mingjun Li, Pengjia Li, Shuo Yin, Shixin Chen, Beichen Li, Chong Tong, Jianlei Yang, Tinghuan Chen, Bei Yu, ACM/IEEE Design Automation Conference (DAC), 2024.
   
6. Architectural Implications of GNN Aggregation Programming Abstractions. Yingjie Qi, Jianlei Yang, Ao Zhou, Tong Qiao, Chunming Hu, IEEE Computer Architecture Letters (CAL), 2024.
   
7. DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2024.
   
8. LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators.. Yicheng Huang, Xueyan Wang, Tianao Dai, Jianlei Yang, Zhaojun Lu, Xiaotao Jia, Gang Qu, Weisheng Zhao, IEEE International Test Conference in Asia (ITC-Asia), 2024.
   
9. An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method. Xiaotao Jia, Huiyi Gu, Yuhao Liu, Jianlei Yang, Xueyan Wang, Weitao Pan, Youguang Zhang, Sorin Cotofana, Weisheng Zhao, IEEE Transactions on Neural Networks and Learning Systems (TNNLS), 2024.

2023:

1. Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms. Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu, ACM/IEEE Design Automation Conference (DAC), 2023.
   
2. Lossy and Lossless (L2) Post-training Model Size Compression. Yumeng Shi, Shihao Bai, Xiuying Wei, Ruihao Gong, Jianlei Yang, International Conference on Computer Vision (ICCV), 2023.
   
3. NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration. Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao, Science China Information Sciences (SCIS), 2023.
   
4. IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations. Yuntao Wei, Xueyan Wang, Shangtong Zhang, Jianlei Yang, Xiaotao Jia, Zhaohao Wang, Gang Qu, Weisheng Zhao, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2023.

2022:

1. Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform. Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu and Weisheng Zhao, ACM/IEEE Design Automation Conference (DAC), 2022.
   
2. Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM. Zhengyi Hou, Zhaohao Wang, Chao Wang, Min Wang, You Wang, Xueyan Wang, Cenlin Duan, Jianlei Yang, IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I), 2022.
   
3. NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration. Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao, SCIENCE CHINA Information Science (SCIS), 2022.
   
4. Accelerating Graph Connected Component Computation with Emerging Processing-In-Memory Architecture. Xuhang Chen, Xueyan Wang, Xiaotao Jia, Jianlei Yang, Gang Qu, Weisheng Zhao, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022.
   
5. NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration. Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao, SCIENCE CHINA Information Science (SCIS), 2022.
   
6. Accelerating Graph Connected Component Computation with Emerging Processing-In-Memory Architecture. Xuhang Chen, Xueyan Wang, Xiaotao Jia, Jianlei Yang, Gang Qu, Weisheng Zhao, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2022.
   
7. S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks. Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao, IEEE Transactions on Computers (TC), 2022.

2021:

1. FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update. Junyu Luo, Jianlei Yang, Xucheng Ye, Xin Guo, Weisheng Zhao, Conference on Information and Knowledge Management (CIKM), 2021. [Code]
   
2. Optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms. Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu, Real-Time and Embedded Technology and Applications Symposium (RTAS), 2021. [Code]
   
3. Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao, IEEE Transactions on Computers (TC), 2021.
   
4. Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao, IEEE Transactions on Neural Networks and Learning Systems (TNNLS), 2021.

2020:

1. Accelerating CNN Training by Pruning Activation Gradients. Xucheng Ye, Pengcheng Dai, Junyu Luo, Xin Guo, Yingjie Qi, Jianlei Yang, Yiran Chen, European Conference on Computer Vision (ECCV), 2020.
   
2. Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method. Chao Wang, Zhaohao Wang, Yansong Xu, Jianlei Yang, Youguang Zhang, International Symposium on Circuits and Systems (ISCAS), 2020.
   
3. Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures. Jianlei Yang, Xiaopeng Gao, Weisheng Zhao, Great Lakes Symposium on VLSI (GLSVLSI), 2020.
   
4. Dual-Plane Switch Architecture for Time-Triggered Ethernet. Meng Dong, Zhiliang Qiu, Weitao Pan, Hongbin Zhang, Chenglei Kong, Hui Jin, Jianlei Yang, Great Lakes Symposium on VLSI (GLSVLSI), 2020.
   
5. TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework with Anonymized Intermediate Representations. Ang Li, Yixiao Duan, Huanrui Yang, Yiran Chen, Jianlei Yang, ACM Knowledge Discovery and Data Mining (KDD), 2020. Best Student Paper Award
   
6. TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu and Weisheng Zhao, ACM/IEEE Design Automation Conference (DAC), 2020.
   
7. SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen and Weisheng Zhao, ACM/IEEE Design Automation Conference (DAC), 2020.
   
8. Fast Physics-based Electromigration Analysis for Full-chip Networks by Efficient Eigenfunction-based Solution. Xiaoyi Wang, Shaobin Ma, Sheldon X.-D. Tan, Chase Cook, Liang Chen, Jianlei Yang, Wenjian Yu, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2020.
   
9. Hardware Security in Spin-Based Computing-In-Memory: Analysis, Exploits, and Mitigation Techniques. Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao, ACM Journal on Emerging Technologies in Computing Systems (JETC), 2020.
   
10. Prototyping federated learning on edge computing systems. Jianlei Yang, Yixiao Duan, Tong Qiao, Huanyu Zhou, Jingyuan Wang, Weisheng Zhao, Frontiers of Computer Science (FCS), 2020.
    
11. An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing. Yu Pan, Xiaotao Jia, Zhen Cheng, Peng Ouyang, Xueyan Wang, Jianlei Yang, Weisheng Zhao, CCF Transactions on High Performance Computing (CCF HPC), 2020.

2019:

1. Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao, (ISVLSI), 2019.
   
2. eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform. Runze Liu, Jianlei Yang, Yiran Chen, Weisheng Zhao, ACM/IEEE Design Automation Conference (DAC), 2019.
   
3. SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing. Biao Pan, Wang Kang, Xing Chen, Jinyu Bai, Jianlei Yang, Youguang Zhang, Weisheng Zhao, International Symposium on Circuits and Systems (ISCAS), 2019.
   
4. Magnetic Skyrmion-Based Neural Recording System Design for Brain Machine Interface. Biao Pan, Wang Kang, Xing Chen, Jinyu Bai, Jianlei Yang, Sai Li, Youguang Zhang, Weisheng Zhao, International Symposium on Circuits and Systems (ISCAS), 2019.
   
5. A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs with Thermal Consideration. Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, Weisheng Zhao, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019.
   
6. SPINBIS: Spintronics based Bayesian Inference System with Stochastic Computing. Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019.
   
7. Exploiting Spin-Orbit Torque Devices as Reconfigurable Logic for Circuit Obfuscation. Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2019.
   
8. Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. Bi Wu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang, Weisheng Zhao, IEEE Transactions on Circuits and Systems-I: Regular Papers (TCAS-I), 2019.
   
9. Skyrmion-Induced Memristive Magnetic Tunnel Junction for Ternary Neural Network. Biao Pan, Deming Zhang, Xueying Zhang, Haotian Wang, Jinyu Bai, Jianlei Yang, Youguang Zhang, Wang Kang, Weisheng Zhao, IEEE Journal of Electron Devices Society (JED), 2019.
   
10. Redesigning Pipeline When Architecting STT-RAM as Registers in Rad-Hard Environment. Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang, Sustainable Computing: Informatics and Systems (SUSCOM), 2019.

2018:

1. A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao, International Conference on Field-Programmable Technology (FPT), 2018.
   
2. Spintronics based Stochastic Computing for Efficient Bayesian Inference System. Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai (Helen) Li, Weisheng Zhao, Asia and South Pacific Design Automation Conference (ASP-DAC), 2018.
   
3. Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint. Yinglin Zhao, Jianlei Yang, Weisheng Zhao, Aida Todri-Sanial, Yuanqing Cheng, Journal of Computer Science and Technology (JCST), 2018.
   
4. Intelligent identification of two-dimensional nanostructures by machine-learning optical microscopy. Xiaoyang Lin, Zhizhong Si, Wenzhi Fu, Jianlei Yang, Side Guo, Yuan Cao, Jin Zhang, Xinhe Wang, Peng Liu, Kaili Jiang, and Weisheng Zhao, Nano Research, 2018.
   
5. Evaluation of Ultrahigh-Speed Magnetic Memories Using Field-Free Spin-Orbit Torque. Zhaohao Wang, Bi Wu, Zuwei Li, Xiaoyang Lin, Jianlei Yang, Youguang Zhang, Weisheng Zhao, IEEE Transactions on Magnetics (TMAG), 2018.
   
6. Demonstration of Multi-State Memory Device Combining Resistive and Magnetic Switching Behaviors. Yu Zhang, Wenlong Cai, Wang Kang, Jianlei Yang, Erya Deng, You-Guang Zhang, Weisheng Zhao, Dafine Ravelosona, IEEE Electron Device Letters (EDL), 2018.
   
7. Heterogeneous Memristive Devices Enabled by Magnetic Tunnel Junction Nanopillars Surrounded by Resistive Silicon Switches. Yu Zhang, Xiaoyang Lin, Jean‐Paul Adam, Guillaume Agnus, Wang Kang, Wenlong Cai, Jean‐Rene Coudevylle, Nathalie Isac, Jianlei Yang, Huaiwen Yang, Kaihua Cao, Hushan Cui, Deming Zhang, Youguang Zhang, Chao Zhao, Weisheng Zhao, Dafine Ravelosona, Advanced Electronic Materials (AEM), 2018.

2017:

1. Thermosiphon: A Thermal Aware NUCA Architecture for Write Energy Reduction of the STT-MRAM based LLCs. Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao, International Conference on Computer-Aided Design (ICCAD), 2017.
   
2. Power Profile Equalizer: A Lightweight Countermeasure against Side-channel Attack. Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang, International Conference on Computer Design (ICCD), 2017.
   
3. Generative adversarial network based scalable on-chip noise sensor placement. Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi, ACM Symposium on Cloud Computing (SoCC), 2017.
   
4. Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment. Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang, (ICESS), 2017. Best Paper Award
   
5. On-chip microfluid induced by oscillation of microrobot for noncontact cell transportation. Lin Feng, Shuzhang Liang, Xiangcong Zhou, Jianlei Yang, Yonggang Jiang, Deyuan Zhang, Fumihito Arai, Applied Physics Letters (APL), 2017.

2015-2016:

1. ODESY: a novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY. Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie, International Conference on Computer-Aided Design (ICCAD), 2016.
   
2. A novel circuit design of true random number generator using magnetic tunnel junction. You Wang, Hao Cai, Lirida A B Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao, IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2016.
   
3. A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy. Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell, Hai Li, (ISVLSI), 2016.
   
4. Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu, Great Lakes Symposium on VLSI (GLSVLSI), 2016.
   
5. Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM. Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao, IEEE Transactions on Reliability (TR), 2016.
   
6. Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect. Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2016.
   
7. Spintronic Memristor as Interface Between DNA and Solid State Devices. Jianlei Yang, Zhenyu Sun, Xiaobin Wang, Yiran Chen, Hai Li, IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), 2016.
   
8. Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), 2016.
   
9. An overview on memristor crossabr based neuromorphic circuit and architecture. Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang, Hai Li, (VLSI-SoC), 2015.
   
10. A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li, Weisheng Zhao, Pierre Chor-Fung Chia, Great Lakes Symposium on VLSI (GLSVLSI), 2015. Best Paper Nomination
    
11. Early Stage Real-Time SoC Power Estimation Using RTL Instrumentation. Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai, Asia and South Pacific Design Automation Conference (ASP-DAC), 2015.

2014 & Before:

1. Power Supply Noise Aware Evaluation Framework for Side Channel Attacks and Countermeasures. Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou, International Conference on Field-Programmable Technology (FPT), 2014. Invited Paper by Special Session of Hardware Security
   
2. Fast Vectorless Power Grid Verification using Maximum Voltage Drop Location Estimation. Wei Zhao, Yici Cai, Jianlei Yang, Asia and South Pacific Design Automation Conference (ASP-DAC), 2014.
   
3. Selected Inversion for Vectorless Power Grid Verification by Exploiting Locality. Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao, International Conference on Computer Design (ICCD), 2013. Best Paper Award
   
4. A Multilevel H-matrix-based Approximate Matrix Inversion Algorithm for Vectorless Power Grid Verification. Wei Zhao, Yici Cai, Jianlei Yang, Asia and South Pacific Design Automation Conference (ASP-DAC), 2013.
   
5. PowerRush: Efficient Transient Simulation for Power Grid Analysis. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou, International Conference on Computer-Aided Design (ICCAD), 2012. Invited Paper by Special Session of Power grid simulation and verification for billion-transistor VLSI designs
   
6. PowerRush: A Linear Simulator for Power Grid. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou, International Conference on Computer-Aided Design (ICCAD), 2011. Invited Paper by Special Session of 2011 TAU Power Grid Contest
   
7. Fast Poisson Solver Preconditioned Method for Robust Power Grid Analysis. Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi, International Conference on Computer-Aided Design (ICCAD), 2011.
   
8. Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin-Ngai Sze, Great Lakes Symposium on VLSI (GLSVLSI), 2011.
   
9. A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification. Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2015.
   
10. PowerRush: An Efficient Simulator for Static Power Grid Analysis. Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2014.
    
11. Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi, IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), 2014.