Xingzhou Cheng

Latest

• NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration
• S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks
• SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training
• TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture