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Weisheng Zhao
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NAND-SPIN-Based Processing-in-MRAM Architecture for Convolutional Neural Network Acceleration
Accelerating Graph Connected Component Computation with Emerging Processing-In-Memory Architecture
Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform
Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture
FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update
S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks
optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms
Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures
Hardware Security in Spin-Based Computing-In-Memory: Analysis, Exploits, and Mitigation Techniques
An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing
Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization
Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy
Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration
eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform
Magnetic Skyrmion-Based Neural Recording System Design for Brain Machine Interface
SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing
Skyrmion-Induced Memristive Magnetic Tunnel Junction for Ternary Neural Network
A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs with Thermal Consideration
SPINBIS: Spintronics based Bayesian Inference System with Stochastic Computing
A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform
Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint
Evaluation of Ultrahigh-Speed Magnetic Memories Using Field-Free Spin-Orbit Torque
Demonstration of Multi-State Memory Device Combining Resistive and Magnetic Switching Behaviors
Exploiting Spin-Orbit Torque Devices as Reconfigurable Logic for Circuit Obfuscation
Spintronics based Stochastic Computing for Efficient Bayesian Inference System
Heterogeneous Memristive Devices Enabled by Magnetic Tunnel Junction Nanopillars Surrounded by Resistive Silicon Switches
Thermosiphon: A Thermal Aware NUCA Architecture for Write Energy Reduction of the STT-MRAM based LLCs
Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM
A novel circuit design of true random number generator using magnetic tunnel junction
Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect
Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach
A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback
Prototyping federated learning on edge computing systems
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