Jianlei Yang, Jiacheng Liao, Fanding Lei, Meichen Liu, Lingkun Long, Junyi Chen, Han Wan, Bei Yu, Weisheng Zhao. TinyFormer: Efficient Sparse Transformer Design and Deployment on Tiny Devices. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 73, no. 5 pp. 3350-3362, 2026.
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu. GCoDE: Efficient Device-Edge Co-Inference for GNNs via Architecture-Mapping Co-Search. IEEE Transactions on Computers (TC), vol. 75, no. 1 pp. 58–72, 2026.
Yingjie Qi, Jianlei Yang, Rubing Yang, Cenlin Duan, Xiaolin He, Ziyan He, Weitao Pan, Weisheng Zhao. CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-Based CIM Architectures. IEEE Transactions on Computers (TC), vol. 75, no. 1 pp. 380–394, 2026.
Cenlin Duan, Jianlei Yang, Yikun Wang, Yiou Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao. Efficient SRAM-PIM Co-Design by Joint Exploration of Value-Level and Bit-Level Sparsity. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 45, no. 1 pp. 246–259, 2026.
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Xinming Wei, Cenlin Duan, Weisheng Zhao, Chunming Hu. ACE-GNN: Adaptive GNN Co-Inference With System-Aware Scheduling in Dynamic Edge Environments. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 45, no. 5 pp. 2334–2347, 2026.
Yingjie Qi, Jianlei Yang, Ao Zhou, Tong Qiao, Chunming Hu. Architectural Implications of GNN Aggregation Programming Abstractions. IEEE Computer Architecture Letters (CAL), vol. 23, no. 1 pp. 125–128, 2024.
Ao Zhou, Jianlei Yang, Yingjie Qi, Tong Qiao, Yumeng Shi, Cenlin Duan, Weisheng Zhao, Chunming Hu. HGNAS: Hardware-Aware Graph Neural Architecture Search for Edge Devices. IEEE Transactions on Computers (TC), vol. 73, no. 12 pp. 2693–2707, 2024.
Cenlin Duan, Jianlei Yang, Xiaolin He, Yingjie Qi, Yikun Wang, Yiou Wang, Ziyan He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weitao Pan, Weisheng Zhao. DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 43, no. 3 pp. 906–918, 2024.
Huiyi Gu, Xiaotao Jia, Yuhao Liu, Jianlei Yang, Xueyan Wang, Youguang Zhang, Sorin Dan Cotofana, Weisheng Zhao. CiM-BNN: Computing-in-MRAM Architecture for Stochastic Computing Based Bayesian Neural Network. IEEE Transactions on Emerging Topics in Computing (TETC), vol. 12, no. 4 pp. 980–990, 2024.
Xiaotao Jia, Huiyi Gu, Yuhao Liu, Jianlei Yang, Xueyan Wang, Weitao Pan, Youguang Zhang, Sorin Cotofana, Weisheng Zhao. An Energy-Efficient Bayesian Neural Network Implementation Using Stochastic Computing Method. IEEE Transactions on Neural Networks and Learning Systems (TNNLS), vol. 35, no. 9 pp. 12913–12923, 2024.
Yinglin Zhao, Jianlei Yang, Bing Li, Xingzhou Cheng, Xucheng Ye, Xueyan Wang, Xiaotao Jia, Zhaohao Wang, Youguang Zhang, Weisheng Zhao. NAND-SPIN-based processing-in-MRAM architecture for convolutional neural network acceleration. Science China Information Sciences (SCIS), vol. 66, no. 4, 2023.
Yuntao Wei, Xueyan Wang, Shangtong Zhang, Jianlei Yang, Xiaotao Jia, Zhaohao Wang, Gang Qu, Weisheng Zhao. IMGA: Efficient In-Memory Graph Convolution Network Aggregation With Data Flow Optimizations. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 42, no. 12 pp. 4695–4705, 2023.
Jianlei Yang, Wenzhi Fu, Xingzhou Cheng, Xucheng Ye, Pengcheng Dai, Weisheng Zhao. S² Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks. IEEE Transactions on Computers (TC), vol. 71, no. 6 pp. 1440–1452, 2022.
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Rong Yin, Xuhang Chen, Gang Qu, Weisheng Zhao. Triangle Counting Accelerations: From Algorithm to In-Memory Computing Architecture. IEEE Transactions on Computers (TC), vol. 71, no. 10 pp. 2462–2472, 2022.
Xuhang Chen, Xueyan Wang, Xiaotao Jia, Jianlei Yang, Gang Qu, Weisheng Zhao. Accelerating Graph-Connected Component Computation With Emerging Processing-In-Memory Architecture. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 41, no. 12 pp. 5333–5342, 2022.
Zhengyi Hou, Zhaohao Wang, Chao Wang, Min Wang, You Wang, Xueyan Wang, Cenlin Duan, Jianlei Yang. Reconfigurable and Dynamically Transformable In-Cache-MPUF System With True Randomness Based on the SOT-MRAM. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 69, no. 7 pp. 2694–2706, 2022.
Xiaoyi Wang, Shaobin Ma, Sheldon X.-D. Tan, Chase Cook, Liang Chen, Jianlei Yang, Wenjian Yu. Fast Physics-Based Electromigration Analysis for Full-Chip Networks by Efficient Eigenfunction-Based Solution. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 40, no. 3 pp. 507–520, 2021.
Xiaotao Jia, Jianlei Yang, Runze Liu, Xueyan Wang, Sorin Dan Cotofana, Weisheng Zhao. Efficient Computation Reduction in Bayesian Neural Networks Through Feature Decomposition and Memorization. IEEE Transactions on Neural Networks and Learning Systems (TNNLS), vol. 32, no. 4 pp. 1703–1712, 2021.
Yu Pan, Xiaotao Jia, Zhen Cheng, Peng Ouyang, Xueyan Wang, Jianlei Yang, Weisheng Zhao. An STT-MRAM based reconfigurable computing-in-memory architecture for general purpose computing. CCF Transactions on High Performance Computing (CCF THPC), vol. 2, no. 3 pp. 272–281, 2020.
Jianlei Yang, Yixiao Duan, Tong Qiao, Huanyu Zhou, Jingyuan Wang, Weisheng Zhao. Prototyping federated learning on edge computing systems. Frontiers of Computer Science (FCS), vol. 14, no. 6 pp. 146318, 2020.
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Xiaotao Jia, Gang Qu, Weisheng Zhao. Hardware Security in Spin-based Computing-in-memory: Analysis, Exploits, and Mitigation Techniques. ACM Journal on Emerging Technologies in Computing Systems (JETC), vol. 16, no. 4 pp. 37:1–37:18, 2020.
Xiaotao Jia, Jianlei Yang, Pengcheng Dai, Runze Liu, Yiran Chen, Weisheng Zhao. SPINBIS: Spintronics-Based Bayesian Inference System With Stochastic Computing. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 4 pp. 789–802, 2020.
Bi Wu, Pengcheng Dai, Yuanqing Cheng, Ying Wang, Jianlei Yang, Zhaohao Wang, Dijun Liu, Weisheng Zhao. A Novel High Performance and Energy Efficient NUCA Architecture for STT-MRAM LLCs With Thermal Consideration. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 39, no. 4 pp. 803–815, 2020.
Bi Wu, Weisheng Zhao, Xiaobo Sharon Hu, Pengcheng Dai, Zhaohao Wang, Chao Wang, Ying Wang, Jianlei Yang, Yuanqing Cheng, Dijun Liu, Youguang Zhang. Bulkyflip: A NAND-SPIN-Based Last-Level Cache With Bandwidth-Oriented Write Management Policy. IEEE Transactions on Circuits and Systems I: Regular Papers (TCAS-I), vol. 67-I, no. 1 pp. 108–120, 2020.
Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang. Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment. Sustainable Computing: Informatics and Systems (SUSCOM), vol. 22 pp. 206–218, 2019.
Jianlei Yang, Xueyan Wang, Qiang Zhou, Zhaohao Wang, Hai Li, Yiran Chen, Weisheng Zhao. Exploiting Spin-Orbit Torque Devices As Reconfigurable Logic for Circuit Obfuscation. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 38, no. 1 pp. 57–69, 2019.
Yinglin Zhao, Jianlei Yang, Weisheng Zhao, Aida Todri-Sanial, Yuanqing Cheng. Power Supply Noise Aware Task Scheduling on Homogeneous 3D MPSoCs Considering the Thermal Constraint. Journal of Computer Science and Technology (JCST), vol. 33, no. 5 pp. 966–983, 2018.
Jianlei Yang, Zhenyu Sun, Xiaobin Wang, Yiran Chen, Hai Li. Spintronic Memristor as Interface Between DNA and Solid State Devices. IEEE Journal on Emerging and Selected Topics in Circuits and Systems (JETCAS), vol. 6, no. 2 pp. 212–221, 2016.
Jianlei Yang, Peiyuan Wang, Yaojun Zhang, Yuanqing Cheng, Weisheng Zhao, Yiran Chen, Hai (Helen) Li. Radiation-Induced Soft Error Analysis of STT-MRAM: A Device to Circuit Approach. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol. 35, no. 3 pp. 380–393, 2016.
Bi Wu, Yuanqing Cheng, Jianlei Yang, Aida Todri-Sanial, Weisheng Zhao. Temperature Impact Analysis and Access Reliability Enhancement for 1T1MTJ STT-RAM. IEEE Transactions on Reliability (TRel), vol. 65, no. 4 pp. 1755–1768, 2016.
Yuanqing Cheng, Aida Todri-Sanial, Jianlei Yang, Weisheng Zhao. Alleviating Through-Silicon-Via Electromigration for 3-D Integrated Circuits Taking Advantage of Self-Healing Effect. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 24, no. 11 pp. 3310–3322, 2016.
Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao. A Selected Inversion Approach for Locality Driven Vectorless Power Grid Verification. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 23, no. 11 pp. 2617–2628, 2015.
Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi. Friendly Fast Poisson Solver Preconditioning Technique for Power Grid Analysis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 22, no. 4 pp. 899–912, 2014.
Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: An Efficient Simulator for Static Power Grid Analysis. IEEE Transactions on Very Large Scale Integration (VLSI) Systems (TVLSI), vol. 22, no. 10 pp. 2103–2116, 2014.
Lingkun Long, Rubing Yang, Yushi Huang, Desheng Hui, Ao Zhou, Jianlei Yang. SlimInfer: Accelerating Long-Context LLM Inference via Dynamic Token Pruning. AAAI Conference on Artificial Intelligence (AAAI), 2026.
Xiaolin He, Cenlin Duan, Yingjie Qi, Xiao May, Jianlei Yang. MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator. Asia and South Pacific Design Automation Conference (ASP-DAC), 2026.
Yingjie Qi, Jianlei Yang, Yiou Wang, Yikun Wang, Dayu Wang, Ling Tang, Cenlin Duan, Xiaolin He, Weisheng Zhao. CIMFlow: An Integrated Framework for Systematic Design and Evaluation of Digital CIM Architectures. ACM/IEEE Design Automation Conference (DAC), 2025.
Haiyang Liu, Xueyan Wang, Jianlei Yang, Xiaotao Jia, Gang Qu, Weisheng Zhao. Ultra Energy-Efficient Butterfly Counting in Bipartite Networks via Algorithm-Architecture Co-Optimization. IEEE/ACM International Conference on Computer Aided Design (ICCAD), 2025.
Tong Qiao, Ao Zhou, Yingjie Qi, Yiou Wang, Han Wan, Jianlei Yang, Chunming Hu. Towards Affordable, Adaptive and Automatic GNN Training on CPU-GPU Heterogeneous Platforms. IEEE International Conference on Computer Design (ICCD), 2025.
Tianwei Pan, Tianao Dai, Jianlei Yang, Hongbin Jing, Yang Su, Zeyu Hao, Xiaotao Jia, Chunming Hu, Weisheng Zhao. Finesse: An Agile Design Framework for Pairing-based Cryptography via Software/Hardware Co-Design. ACM/IEEE International Symposium on Computer Architecture (ISCA), 2025.
Ao Zhou, Jianlei Yang, Tong Qiao, Yingjie Qi, Zhi Yang, Weisheng Zhao, Chunming Hu. Graph Neural Networks Automated Design and Deployment on Device-Edge Co-Inference Systems. ACM/IEEE Design Automation Conference (DAC), 2024.
Cenlin Duan, Jianlei Yang, Yiou Wang, Yikun Wang, Yingjie Qi, Xiaolin He, Bonan Yan, Xueyan Wang, Xiaotao Jia, Weisheng Zhao. Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity. ACM/IEEE Design Automation Conference (DAC), 2024.
Mingjun Li, Pengjia Li, Shuo Yin, Shixin Chen, Beichen Li, Chong Tong, Jianlei Yang, Tinghuan Chen, Bei Yu. WinoGen: A Highly Configurable Winograd Convolution IP Generator for Efficient CNN Acceleration on FPGA. ACM/IEEE Design Automation Conference (DAC), 2024.
Tong Qiao, Jianlei Yang, Yingjie Qi, Ao Zhou, Chen Bai, Bei Yu, Weisheng Zhao, Chunming Hu. GNNavigator: Towards Adaptive Training of Graph Neural Networks via Automatic Guideline Exploration. ACM/IEEE Design Automation Conference (DAC), 2024.
Yicheng Huang, Xueyan Wang, Tianao Dai, Jianlei Yang, Zhaojun Lu, Xiaotao Jia, Gang Qu, Weisheng Zhao. LLP-ECCA: A Low-Latency and Programmable Framework for Elliptic Curve Cryptography Accelerators. IEEE International Test Conference in Asia (ITC-Asia), 2024.
Ao Zhou, Jianlei Yang, Yingjie Qi, Yumeng Shi, Tong Qiao, Weisheng Zhao, Chunming Hu. Hardware-Aware Graph Neural Network Automated Design for Edge Computing Platforms. ACM/IEEE Design Automation Conference (DAC), 2023.
Yumeng Shi, Shihao Bai, Xiuying Wei, Ruihao Gong, Jianlei Yang. Lossy and Lossless (L²) Post-training Model Size Compression. IEEE/CVF International Conference on Computer Vision (ICCV), 2023.
Mingjun Li, Jianlei Yang, Yingjie Qi, Meng Dong, Yuhao Yang, Runze Liu, Weitao Pan, Bei Yu, Weisheng Zhao. Eventor: An Efficient Event-Based Monocular Multi-View Stereo Accelerator on FPGA Platform. ACM/IEEE Design Automation Conference (DAC), 2022.
Han Wan, Hongzhen Luo, Zihao Zhong, Jianlei Yang. Exploring the Factors of Students’ Online Learning Based On Structural Equation Modeling. IEEE International Conference on Teaching, Assessment and Learning for Engineering (TALE), 2022.
Junyu Luo, Jianlei Yang, Xucheng Ye, Xin Guo, Weisheng Zhao. FedSkel: Efficient Federated Learning on Heterogeneous Systems with Skeleton Gradients Update. ACM International Conference on Information and Knowledge Management (CIKM), 2021.
Ao Zhou, Jianlei Yang, Yeqi Gao, Tong Qiao, Yingjie Qi, Xiaoyi Wang, Yunli Chen, Pengcheng Dai, Weisheng Zhao, Chunming Hu. Optimizing Memory Efficiency of Graph Neural Networks on Edge Computing Platforms. IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS), 2021.
Pengcheng Dai, Jianlei Yang, Xucheng Ye, Xingzhou Cheng, Junyu Luo, Linghao Song, Yiran Chen, Weisheng Zhao. SparseTrain: Exploiting Dataflow Sparsity for Efficient Convolutional Neural Networks Training. ACM/IEEE Design Automation Conference (DAC), 2020.
Xueyan Wang, Jianlei Yang, Yinglin Zhao, Yingjie Qi, Meichen Liu, Xingzhou Cheng, Xiaotao Jia, Xiaoming Chen, Gang Qu, Weisheng Zhao. TCIM: Triangle Counting Acceleration With Processing-In-MRAM Architecture. ACM/IEEE Design Automation Conference (DAC), 2020.
Xucheng Ye, Pengcheng Dai, Junyu Luo, Xin Guo, Yingjie Qi, Jianlei Yang, Yiran Chen. Accelerating CNN Training by Pruning Activation Gradients. European Conference on Computer Vision (ECCV), 2020.
Meng Dong, Zhiliang Qiu, Weitao Pan, Hongbin Zhang, Chenglei Kong, Hui Jin, Jianlei Yang. Dual-Plane Switch Architecture for Time-Triggered Ethernet. Great Lakes Symposium on VLSI (GLSVLSI), 2020.
Jianlei Yang, Xiaopeng Gao, Weisheng Zhao. Towards Systems Education for Artificial Intelligence: A Course Practice in Intelligent Computing Architectures. Great Lakes Symposium on VLSI (GLSVLSI), 2020.
Chao Wang, Zhaohao Wang, Yansong Xu, Jianlei Yang, Youguang Zhang, Weisheng Zhao. Computing-in-Memory Architecture Based on Field-Free SOT-MRAM with Self-Reference Method. IEEE International Symposium on Circuits and Systems (ISCAS), 2020.
Ang Li, Yixiao Duan, Huanrui Yang, Yiran Chen, Jianlei Yang. TIPRDC: Task-Independent Privacy-Respecting Data Crowdsourcing Framework for Deep Learning with Anonymized Intermediate Representations. ACM SIGKDD Conference on Knowledge Discovery and Data Mining (KDD), 2020 (Best Student Paper Award).
Runze Liu, Jianlei Yang, Yiran Chen, Weisheng Zhao. eSLAM: An Energy-Efficient Accelerator for Real-Time ORB-SLAM on FPGA Platform. ACM/IEEE Design Automation Conference (DAC), 2019.
Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Sai Li, Youguang Zhang, Weisheng Zhao. Magnetic Skyrmion-Based Neural Recording System Design for Brain Machine Interface. IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
Biao Pan, Kang Wang, Xing Chen, Jinyu Bai, Jianlei Yang, Youguang Zhang, Weisheng Zhao. SR-WTA: Skyrmion Racing Winner-Takes-All Module for Spiking Neural Computing. IEEE International Symposium on Circuits and Systems (ISCAS), 2019.
Yinglin Zhao, Jianlei Yang, Xiaotao Jia, Xueyan Wang, Zhaohao Wang, Wang Kang, Youguang Zhang, Weisheng Zhao. Exploiting Near-Memory Processing Architectures for Bayesian Neural Networks Acceleration. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2019.
Xiaotao Jia, Jianlei Yang, Zhaohao Wang, Yiran Chen, Hai Helen Li, Weisheng Zhao. Spintronics based stochastic computing for efficient Bayesian inference system. Asia and South Pacific Design Automation Conference (ASP-DAC), 2018.
Xufeng Li, Jianlei Yang, Richong Zhang, Hongyuan Ma. A Novel Approach on Entity Linking for Encyclopedia Infoboxes. China Conference on Knowledge Graph and Semantic Computing (CCKS), 2018.
Wenzhi Fu, Jianlei Yang, Pengcheng Dai, Yiran Chen, Weisheng Zhao. A Scalable Pipelined Dataflow Accelerator for Object Region Proposals on FPGA Platform. International Conference on Field-Programmable Technology (FPT), 2018.
Bi Wu, Yuanqing Cheng, Pengcheng Dai, Jianlei Yang, Youguang Zhang, Dijun Liu, Ying Wang, Weisheng Zhao. Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2017.
Chenguang Wang, Ming Yan, Yici Cai, Qiang Zhou, Jianlei Yang. Power Profile Equalizer: A Lightweight Countermeasure against Side-Channel Attack. IEEE International Conference on Computer Design (ICCD), 2017.
Jinglan Liu, Yukun Ding, Jianlei Yang, Ulf Schlichtmann, Yiyu Shi. Generative adversarial network based scalable on-chip noise sensor placement. IEEE International System-on-Chip Conference (SOCC), 2017.
Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu, Jianlei Yang. Pipeline Optimizations of Architecting STT-RAM as Registers in Rad-Hard Environment. IEEE Trustcom/BigDataSE/ICESS (TrustCom), 2017 (Best Paper Award).
Xueyan Wang, Xiaotao Jia, Qiang Zhou, Yici Cai, Jianlei Yang, Mingze Gao, Gang Qu. Secure and Low-Overhead Circuit Obfuscation Technique with Multiplexers. Great Lakes Symposium on VLSI (GLSVLSI), 2016.
Linuo Xue, Yuanqing Cheng, Jianlei Yang, Peiyuan Wang, Yuan Xie. ODESY: A novel 3T-3MTJ cell design with optimized area DEnsity, scalability and latencY. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2016.
Chenchen Liu, Qing Yang, Bonan Yan, Jianlei Yang, Xiaocong Du, Weijie Zhu, Hao Jiang, Qing Wu, Mark Barnell, Hai Li. A Memristor Crossbar Based Computing Engine Optimized for High Speed and Accuracy. IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 2016.
You Wang, Hao Cai, Lirida A. B. Naviner, Jacques-Olivier Klein, Jianlei Yang, Weisheng Zhao. A novel circuit design of true random number generator using magnetic tunnel junction. IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH), 2016.
Jianlei Yang, Liwei Ma, Kang Zhao, Yici Cai, Tin-Fook Ngai. Early stage real-time SoC power estimation using RTL instrumentation. Asia and South Pacific Design Automation Conference (ASP-DAC), 2015.
Bonan Yan, Zheng Li, Yaojun Zhang, Jianlei Yang, Hai Li, Weisheng Zhao, Pierre Chor-Fung Chia. A High-Speed Robust NVM-TCAM Design Using Body Bias Feedback. Great Lakes Symposium on VLSI (GLSVLSI), 2015 (Best Paper Award Nomination).
Zheng Li, Chenchen Liu, Yandan Wang, Bonan Yan, Chaofei Yang, Jianlei Yang, Hai Li. An overview on memristor crossbar based neuromorphic circuit and architecture. IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), 2015.
Wei Zhao, Yici Cai, Jianlei Yang. Fast vectorless power grid verification using maximum voltage drop location estimation. Asia and South Pacific Design Automation Conference (ASP-DAC), 2014.
Jianlei Yang, Chenguang Wang, Yici Cai, Qiang Zhou. Power supply noise aware evaluation framework for side channel attacks and countermeasures. International Conference on Field-Programmable Technology (FPT), 2014.
Wei Zhao, Yici Cai, Jianlei Yang. A multilevel H-matrix-based approximate matrix inversion algorithm for vectorless power grid verification. Asia and South Pacific Design Automation Conference (ASP-DAC), 2013.
Jianlei Yang, Yici Cai, Qiang Zhou, Wei Zhao. Selected inversion for vectorless power grid verification by exploiting locality. IEEE International Conference on Computer Design (ICCD), 2013 (Best Paper Award).
Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: Efficient transient simulation for power grid analysis. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2012.
Feifei Niu, Qiang Zhou, Hailong Yao, Yici Cai, Jianlei Yang, Chin Ngai Sze. Obstacle-avoiding and slew-constrained buffered clock tree synthesis for skew optimization. ACM Great Lakes Symposium on VLSI (GLSVLSI), 2011.
Jianlei Yang, Zuowei Li, Yici Cai, Qiang Zhou. PowerRush: A linear simulator for power grid. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011.
Jianlei Yang, Yici Cai, Qiang Zhou, Jin Shi. Fast poisson solver preconditioned method for robust power grid analysis. IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 2011.