IEEE TCAD paper on SRAM-PIM co-design with joint value-level and bit-level sparsity

👏 Paper title: Efficient SRAM-PIM Co-Design by Joint Exploration of Value-Level and Bit-Level Sparsity.

This work explores sparsity in SRAM-based processing-in-memory at two complementary levels. Value-level sparsity can skip zero operands, while bit-level sparsity can remove unnecessary operations inside nonzero numerical values. Treating only one level leaves useful efficiency opportunities unused.

The proposed co-design jointly exploits structured zero values and unstructured zero bits in digital SRAM-PIM arrays. By aligning sparsity-aware algorithms with hardware execution, the framework reduces redundant computation and improves accelerator efficiency beyond what single-level sparsity optimization can provide.

This work is motivated by the observation that different kinds of sparsity appear at different layers of the computation. Value-level sparsity removes entire operands, while bit-level sparsity can still reduce work inside remaining nonzero values.

By combining both views, the co-design exposes more optimization opportunities for SRAM-PIM arrays. It also provides a more complete framework for sparse DNN acceleration, where model-level pruning and hardware-level bit operations need to be optimized together.