CIMinus accepted by IEEE TC: sparse DNN workload modeling and exploration for SRAM-based CIM

👏 Paper title: CIMinus: Empowering Sparse DNN Workloads Modeling and Exploration on SRAM-based CIM Architectures.

CIMinus provides a systematic modeling framework for sparse DNN workloads on SRAM-based compute-in-memory architectures. Although sparsity is a major opportunity for reducing neural network cost, CIM arrays impose rigid mapping and dataflow constraints that make sparse execution difficult to evaluate.

The framework models workload latency and component-level energy consumption under diverse sparsity patterns and multi-macro CIM mappings. With its sparsity abstraction and pruning-to-evaluation workflow, CIMinus helps designers understand when sparsity leads to real system benefits and how mapping strategies should be chosen for practical CIM accelerators.

CIMinus is motivated by the gap between sparse model compression and hardware-realistic evaluation. A sparse network may contain fewer operations on paper, but the actual benefit depends on whether the CIM architecture can exploit that sparsity efficiently.

By connecting sparsity patterns, pruning strategies, and architecture-level cost models, CIMinus gives designers a way to evaluate sparse DNN workloads before committing to a hardware design. This supports more informed accelerator exploration and avoids overly optimistic sparsity assumptions.