MIREDO accepted by ASP-DAC 2026: MIP-driven dataflow optimization for CIM accelerators

👏 Paper title: MIREDO: MIP-Driven Resource-Efficient Dataflow Optimization for Computing-in-Memory Accelerator.

MIREDO focuses on dataflow optimization for computing-in-memory accelerators. CIM architectures can reduce data movement for DNN workloads, but their practical efficiency depends strongly on how workloads are mapped under strict array, transfer, and architectural constraints.

The framework formulates dataflow optimization as a mixed-integer programming problem. It combines a hierarchical hardware abstraction with an analytical latency model so that workload characteristics, dataflow choices, and CIM-specific constraints can be optimized together. This systematic search helps close the gap between theoretical CIM capability and actual system-level performance.

MIREDO is useful because CIM accelerators often have many hidden constraints: array capacity, memory hierarchy, interconnect cost, operand placement, and data reuse all affect performance. A dataflow that looks efficient at the algorithm level may be inefficient once these hardware limits are considered.

By expressing the optimization problem formally, MIREDO can search this design space more systematically than hand-tuned heuristics. The framework helps identify mappings that use CIM resources effectively and provides a clearer methodology for comparing accelerator configurations.