DB-PIM accepted by DAC 2024: exploiting unstructured bit-level sparsity for efficient SRAM-PIM design

👏 Paper title: Towards Efficient SRAM-PIM Architecture Design by Exploiting Unstructured Bit-Level Sparsity.

DB-PIM improves digital SRAM-PIM by looking beneath value-level sparsity and exploiting sparsity at the bit level. Many neural network operands contain redundant zero bits even when the values themselves are not zero, creating an opportunity for finer-grained acceleration.

The framework combines sparsity-preserving algorithm choices with hardware support such as dyadic block multiplication units and CSD-based adder trees. This co-design reduces unnecessary bit-level computation and improves performance and energy efficiency for SRAM-PIM accelerators.

This work expands the notion of sparsity from zero values to sparse bit patterns inside numerical representations. That distinction matters for PIM arrays because bit-serial or bit-parallel operations can waste energy on redundant zero bits even when the stored value is nonzero.

DB-PIM therefore connects algorithmic sparsity preservation with hardware mechanisms that can benefit from it. The result is a more fine-grained optimization path for SRAM-PIM architectures, especially for neural network workloads with rich bit-level redundancy.