DDC-PIM accepted by IEEE TCAD: doubling effective data capacity for SRAM-based processing-in-memory

👏 Paper title: DDC-PIM: Efficient Algorithm/Architecture Co-Design for Doubling Data Capacity of SRAM-Based Processing-in-Memory.

DDC-PIM targets a central limitation of SRAM-based processing-in-memory: the tight relationship between array capacity and computable data placement. While SRAM-PIM can reduce data movement, practical designs must still fit operands and intermediate data into limited array resources.

The paper exploits the cross-coupled structure of 6T SRAM cells to store and use complementary bit pairs more efficiently. Through algorithm and architecture co-design, DDC-PIM increases effective data capacity for SRAM-PIM arrays and improves the practicality of in-memory DNN acceleration.

The work is especially relevant because many SRAM-PIM optimizations are constrained by how data must be placed inside memory arrays. Improving effective capacity can reduce data remapping, array pressure, and unnecessary movement between compute and storage regions.

DDC-PIM shows how circuit-level properties and algorithm-level mapping can reinforce one another. This makes it a representative example of why PIM design often needs joint reasoning across devices, arrays, data representation, and neural network computation.