S2Engine accepted by IEEE TC: a systolic architecture for sparse convolutional neural networks

👏 Paper title: S2Engine: A Novel Systolic Architecture for Sparse Convolutional Neural Networks.

S2Engine targets the challenge of accelerating sparse convolutional neural networks while retaining the regular dataflow advantages of systolic arrays. Sparse CNNs can reduce arithmetic work, but irregular nonzero patterns often make hardware utilization and data reuse difficult.

The architecture coordinates sparse computation, data reuse, and array-level scheduling so that sparsity can be exploited without sacrificing the scalability of systolic execution. This design improves inference efficiency for sparse CNN workloads and offers a hardware-friendly path for deploying compact neural networks.

S2Engine is important because sparse neural networks often create irregular execution patterns that conventional accelerators handle poorly. The design keeps computation structured enough for systolic processing while still skipping redundant work introduced by sparsity.

By bridging sparsity and regular array execution, the architecture supports efficient CNN inference for compressed models. This makes it relevant to accelerator designs that need high utilization, predictable data movement, and support for increasingly sparse DNN workloads.